1. Field of the Invention
The invention relates generally to data transfer, and in particular to data transfer through a bus or a system controller.
2. Discussion of the Related Art
As workstation and server systems use more and more DRAM memory, the physical and logical lengths of the channels between the system memory controller and the DRAM devices themselves are becoming longer. As a result, the transit time of data between the memory controller and the DRAMs is increasing. When this happens on a system that uses a single channel for both read and write data, xe2x80x9cturning the bus aroundxe2x80x9d between the read data and the write data results in more substantial periods during which no data is valid at one end of the chain or the other. This is a waste of DRAM channel bandwidth.
The traditional technique for minimizing wasted bandwidth is to enforce long write bursts and long read bursts. This increases the amount of time that data is being pipelined through the channel and decreases the amount of time that is spent in transition.
Unfortunately, a memory controller that solves the problem of wasted bandwidth in this way is quickly saddled with the problem of elevated system memory read latency, because the performance of a device demanding data is often degraded more by latency increase than by memory bandwidth deficiencies.
So far, this problem has been solved with static methods that pre-specify the minimum size of the write burst. However, optimizing the system for low latency (worst case of 2 additional cycles) can cause system bandwidth to be degraded to 40% of the theoretical bandwidth; conversely, optimizing for only a 28% bandwidth loss can cause a latency hit of up to 8 cycles. Both of these circumstances are aggravated in the worst case: when the memory controller is receiving requests that cause it to perform the same number of DRAM write transactions as DRAM read transactions.
In one embodiment, monitoring data traffic through a memory controller; and dynamically and automatically selecting a burst length for data transactions through a memory controller in response to the monitored data traffic is disclosed.